Electrical engineers have traditionally referred to the channel length of a surface FET as the lateral distance between the source and drain regions. For example, A. S. Grove, "Physics and Technology of Semiconductor Devices", John Wiley & Sons, 1967, pages 276 and 331 show this channel length reference. This description of the channel length was adequate when FET device measurements of such factors as threshold voltage were correlated with junction bevel and stain results for long channel devices having a channel length of greater than 10 microns. The advent of shorter channel devices having a channel length of shorter than 5 microns resulted in no correlation with the bevel and stain method, due to the unreliability of the bevel and stain metallurgical delineation technique.
Junction delineation by electron-beam induced current measurement in a scanning electron microscope has become necessary. A surface field effect transistor is bevel sectioned at some shallow angle, say 10 degrees, preserving electrical contact to the source and drain diffusions, the gate, and the substrate. The chip is mounted on a TO-5 header and these four contacts are wire bonded to the header. This device is then placed in the scanning electron microscope (SEM) equipped to do electron beam induced current (EBIC) measurements. The device is connected to the EBIC current amplifier with the source and drain as inputs, and the gate and substrate as ground. With the brightness modulation mode of the SEM, a micrograph of the source and drain junctions is obtained. The distance between the two junctions is referred to as the channel length. With the line scan mode of the SEM, a trace of the source and drain junctions is obtained.
While this method is more reliable than the bevel and stain method, it has been found by the inventor of the present invention that the measurement does not give the true electrical channel length because, when both source and drain diffusions are connected in parallel, the depletion region of one junction is altered by the junction potential of the other. The electron beam induced current is generated when the hole-electron pairs generated by the electron beam striking the depletion region are swept out by the existing junction potential. Thus, when the depletion region of one junction is altered by the junction potential of the other, the EBIC indicates the altered junction.
"Junction Depth Measurements in A Scanning Electron Microscope" by J. D. Schick, published in Electron and Ion Beam Science and Technology Sixth International Conference, pages 177-187 describes a method for measuring junction depths of shallow bipolar devices utilizing EBIC signal. Measurement of the channel length of a FET is not disclosed. "Failure Analysis of Integrated Circuits With SEM Beam Induced Currents" by J. D. Schick, published in Scanning Electron Microscopy/1974 (Part IV), Proceedings of the Workshop on Failure Analysis and the SEM IIT Research Institute, pages 949-954 teaches that EBIC measurement can be used for locating failures in high density integrated circuits, identifying leakage paths in devices, measuring junction depths and base widths, and obtaining diffusion concentration profiles.
"Determining Doping Levels in Silicon Devices", IBM Technical Disclosure Bulletin, Vol. 17, No. 8, January 1975, pages 2299-2300 teaches that a scanning electron microscope EBIC measurement allows a determination of doping concentrations and also of variations of doping in a device.
"Junction Depth Measurement by An Electron Beam", IBM Technical Disclosure Bulletin, Vol. 13, No. 3, August 1970, page 675 discloses the technique to determine the depth of a PN junction by means of EBIC measurement.